REBEL-6: A 32-trit balanced ternary instruction set architecture with R2R compiler pipeline for C
Steven Bos, Vetle Bodahl, Ole Christian Moholth, Henning Gundersen · 2025
Is a symmetrical ternary radix more efficient for computing than an asymmetrical binary one? In this work a novel balanced ternary instruction set architecture (ISA) called REBEL-6 is presented with unique features such as three-way comparison and branching, majority voting, rounding and RV32I (binary) compatibility. An open source RV32I to REBEL (R2R) compiler pipeline for C programs is provided. The 32-trit REBEL-6 ISA can be directly compared to a 32-bit RV32I ISA. Preliminary benchmarks show a 1.4% reduction in instruction executions and 33.2% reduction in dynamic power consumption due to improvements in information density and state switching.