Side Channel Power Attack Dataset Characterization for Secure Adiabatic Circuit Level VLSI Abstraction
V. Harynee, G.K. Bhuvanesh, Anjana Jyothi Banu, A. Prathiba · 2024
The primary objective of this paper is to compile a benchmark dataset of power traces to evaluate side channel power attack analysis on Charge Balancing Symmetric Pre-resolve Adiabatic Logic (CBSPAL) named as, CBSPAL-Side Channel Attack (CBSPAL-SCA). CBSPAL and its related secure adiabatic logic styles in literature has been popular towards its resilience against the differential, correlation and other statistical attack approaches. This CBSPAL-SCA dataset is collected through the circuit level VLSI implementation during the Round 1 execution of the PRESENT Algorithm in CBSPAL. The inputs for the circuit-level design (plaintext and key) are generated using Python scripts, producing fixed key and random plaintext pairs. We collected 20,000 power traces for the fixed first key 1 and 30,000 for the fixed second key 2, resulting in a total of 50,000 power traces. The metadata information for different power leakage modeling has been provided. The leakage power traces dataset will be highly useful for the research community to perform side channel power attack analysis, the first one reportedly on the circuit level VLSI implementation. The practical applications of CBSPAL datasets include cryptographic vulnerability analysis, forensics and security audits, benchmarking security implementations, research in machine learning for SCAs, evaluation of low-power cryptographic designs, and educational use. The practical applications of CBSPAL datasets include cryptographic vulnerability analysis, forensics and security audits, benchmarking security implementations, research in machine learning for SCAs, evaluation of low-power cryptographic designs, and educational use.