Application of explainable AI on deep learning-based gate length scalable IV parameter extractor for BSIM-IMG
Fredo Chavez, Jen-Hao Chen, Chien-Ting Tung, Chenming Calvin Hu, Sourabh Khandelwal · Solid-State Electronics · 2025
A new deep-learning(DL) based gate length scalable I-V parameter extraction technique for FDSOI technology on industry-standard BSIM-IMG compact model is presented. For the first time, the learning quality of DL extractors has been studied using an explainable AI technique called SHapley Additive exPlanations (SHAP). Through analysis, it is shown that the single-step DL parameter extraction can get deviated by less relevant relationships between the I − V region and the BSIM-IMG parameters. A multi-step DL extraction is then designed by applying expertise in BSIM-IMG model parameters. The multi-step DL extractor has a customized DL architecture that forces the DL model to learn the relevant relationship between the input I D datapoint and the BSIM-IMG parameters. The single- and multi-step DL extraction has been tested for measured data with gate-lengths ( L G ) ranging from 52 nm to 961 nm. The multi-step DL extractor shows better accuracy in I-V and better scaling to the key electrical parameters as compared to the single-step DL parameter extraction. The developed solution has improved the accuracy, shortened extraction time, reduced the complexity, and can assist in very fast scalable model generation for FDSOI technologies.