Design and FPGA Implementation of a 4-Bit ALU Using Reversible Logic Gates
Yug Milind Thosar · International Journal for Research in Applied Science and Engineering Technology · 2025
Reversible computing offers a promising approach to mitigate the power dissipation challenges inherent in conventional digital systems. In this work, we present the design and analysis of a novel 4-bit reversible Arithmetic Logic Unit (ALU) that leverages reversible logic gates—including Fredkin, Feynman, Universal Reversible Gate (URG), and ThapliyalSrinivas Gate (TSG)—to perform a suite of fundamental arithmetic and logical operations. The ALU is architected to execute operations such as binary addition, subtraction, logical AND, OR, and NOT under a unified reversible computing framework, thereby ensuring a one-one mapping between inputs and outputs and minimizing energy loss due to information erasure. To validate the design, the complete system was modeled using MATLAB Simulink and further synthesized to VHDL code, with implementation on a BASYS-3 FPGA featuring a Xilinx ARTIX-7 device. Comprehensive simulation results demonstrate the circuit’s functional correctness and favorable performance in terms of resource utilization and power consumption. The study also includes performance analysis highlighting the low usage of Look-Up Tables (LUTs) and flip-flops and identifies potential avenues for further optimization, including reductions in quantum cost and propagation delay. The proposed reversible ALU underscores the practicality of energy-efficient, reversible logic in real-world VLSI and quantum-aware architectures, thus opening new possibilities for sustainable computing technology