Innovative V-NAND Flash Structure with Dual Trap Layer for Future Generations of Multi-Bit Device
Jeongyoon Yeo, Joonsung Kim, Younghwan Son, Taein Lee, Sejun Park, Min-Kyu Jeong, Jung Hoon Lee, Suk‐Kang Sung, Dongku Kang, Seungwan Hong, Sung Hoi Hur · 2025
The primary strategy for high-capacity storage NAND flash memory is to increase the number of bits per cell without process-related hardship. The novel vertical NAND (V-NAND) flash structure with a back gate and a pair of trap (Dual Trap) layers facing a single channel can create more levels of VTH and expand erase-program (E/P) VTH window per cell. Conventional cell operating schemes are changed to control each specific cell area with the back gate structure. Technology Computer-Aided Design (TCAD) simulation tool is used to examine cell operations in the proposed structure, demonstrating its superiority in terms of creating higher bit density with advanced cell reliability.