Enhanced I2C Architecture With Integrated CRC for Error Detection in Multi-Slave Systems
M. Suchitra, D L Girijamba, B Gokul, S. Parameshwara · 2025
Modern embedded systems and IoT devices are based on the requirement of reliable data communication; errors may lead to system malfunctions. Therefore, in this work, a Cyclic Redundancy Check mechanism is integrated into the communication process to overcome the limitations of the standard Inter-Integrated Circuit ($\mathrm{I}^{2} \mathrm{C}$) protocol. The improved design is based on data integrity through verification of the transmitted data between the master and multiple slave devices. It can handle the minimal error-checking capability of traditional$\mathrm{I}^{2} \mathrm{C}$implementations. The architecture remains fully compatible with existing$I^{2} C$standards but adds a layer of robustness against data corruption and noise. Simulation results confirm significant improvements in error detection and reliability without considerable complexity or resource overhead. This enhancement makes the improved$\mathbf{I}^{\mathbf{2}} \mathbf{C}$protocol a perfect solution for applications that require secure, stable, and efficient communication, especially in environments where reliable data transfer is a top priority. The approach gives a practical advancement for future embedded and IoT communication systems.