Cutting Edge Design of High Performance Dadda Multipiler for Fast Arithmetic Operations
K. Yogeshwaran, M. Yogesh, B. Nandha Srinivass, M Alagumeenaakshi, P Balasubramanian, S. Veerendiran · 2025
Dadda Multipliers focuses on enhancing the speed and efficiency of arithmetic operations through an optimized design. The Dadda multiplier, renowned for its efficient partial product reduction and minimal delay, is refined using innovative optimization techniques to improve performance. The primary goal is to achieve ultra-fast multiplication by reducing the number of computational steps and minimizing latency, while maintaining accuracy and reliability. Key innovations include an optimized carry-save adder (CSA) structure, an effective carry-propagation mechanism, and an improved partial product matrix reduction algorithm. These enhancements collectively reduce hardware complexity, lower power consumption, and optimize critical path delays. The design's scalability allows it to handle a broad range of operand sizes, making it adaptable for various high-performance digital applications. Comprehensive simulations and FPGA-based synthesis demonstrate significant improvements over conventional multiplier architectures in terms of speed, resource utilization, and energy efficiency. This makes the enhanced Dadda multiplier an ideal solution for modern, high-speed digital systems that require rapid and reliable arithmetic computations. The research highlights the importance of balancing speed, area, and power in achieving an optimized design, contributing valuable insights to the ongoing development of efficient arithmetic circuits.