Design and Analysis of Two-Stage Comparator with Telescopic Amplifier and Dynamic Comparator for Low-Voltage Applications
C R Pooja, Panwala Fenil Chetankumar, H K Ravi · 2025
A novel two stage comparator design that integrates a telescopic amplifier with a conventional single stage dynamic comparator has been presented in this paper. This circuit aims to accomplish an improved offset, good precision and speed that often achieves high performance for numerous applications. Circuit designs, layout and simulations have been done using Cadence virtuoso in 45 nm technology. The designed circuit suppresses the noise by amplifying small input signals that increase the differential gain of the telescopic amplifier up to 98.72, where this improvement observed in the first stage will significantly uplift the overall performance of the comparator. The pre-layout simulation shows that the designed comparator can detect at least 1.306 mV of voltage difference at the input with$V_{\text{cm}, \text { in }}=200 \text{mV}$, whereas the post-layout simulation has 6.4 mV of resolution at$V_{\text{cm}, \text { in }}=200 \text{mV}$. The observed delay of this comparator at the time of pre-layout simulation is 18.49$\mu$s and power consumption is found to be 39.226 nW as well as$23.71 \mu ~\mathrm{s}$of delay and 69.52 nW of power consumption during post-layout simulation with 6.4 mV of voltage difference at the input. With comparable power consumption and lower offset voltage, the suggested two-stage comparator delivers a notable performance boost over traditional designs. Better noise suppression is another benefit of the design, which makes it appropriate for low-power and high-speed applications such as signal processing circuits, instrumentation, high-speed analog-todigital converters (ADCs), and other precision-driven systems that need quick and dependable signal comparison.