Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages
Sudipta Paria, Aritra Dasgupta, Swarup Bhunia · 2025
Modern computing systems rely on System-on-Chips (SoCs) to integrate multiple Intellectual Property (IP) cores developed in-house or acquired from third-party vendors with varying trust levels. Commercial Off-The-Shelf (COTS) components, such as microcontrollers and FPGAs, offer ready-made solutions but introduce security risks, especially in an untrusted supply chain. Effective verification of both IP cores and COTS components is essential for ensuring functionality, security, and reliability. Traditional IP verification techniques are often complex and error-prone due to over-reliance on manual efforts, while COTS verification poses significant challenges due to their inherent black-box nature and diverse integrity issues. The emergence of Large Language Models (LLMs) significantly enhances hardware verification by automating tasks such as code generation and bug fixing. In this paper, we present a review of LLM-based IP verification methods and discuss challenges in current verification practices. Next, we propose an LLM-driven workflow that generates test programs for COTS verification and demonstrate its effectiveness through experimental analysis on open-source COTS processors.