A Low-Power Low-Cost CML-Based Divider-by-2 with Quadrature Outputs
Chen Wang, Ziru Zhang, Yuyang Ding, Bo Zhou · 2024
An RF divider-by-2 with quadrature outputs was designed in 65-nm CMOS technology. The divider consists of two cascaded current-mode logic (CML) latches that are cross- coupled, achieving a frequency range of 2 ~ 9.5 GHz with the sensitivity from −38.9 dBm to 0 dBm. The proposed divider consumes 0.47 mW from a 1.2-V supply and has a core area of 528 µm2. The phase noise of −138.9 dBc/Hz at 1-MHz offset frequency is also accomplished. With tri-state inverter based cross-couple structure, the presented circuit contributes to a low- power low-cost design of RF quadrature signal generators with the phase error less than 1.6°.