A Compact High-Speed Capacitive Data Transfer Link With Common Mode Transient Rejection for Isolated Sensor Interfaces
Isa H. Altoobaji, Ahmad Yusoff Hassan, Mohamed Ali, Yves Audet, Ahmed Lakhssassi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
In this article, a compact differential data transfer link architecture for isolated sensor interfaces (SIs) and immune to common mode transients (CMTs) is presented. The proposed architecture shows low latency supporting high-speed transmission with a low bit error rate (BER) in the presence of CMT noise for applications, such as data acquisition, biomedical equipment, and communication networks. In transportation applications, motors and actuators are subjected to harsh environmental conditions, e.g., lightning strikes and abnormal voltage operations. These conditions introduce noise and can cause damage to small electronics due to high-voltage power surges. To ensure human safety and circuitry protection, a data transfer system must be implemented between high-voltage and low-voltage domains. The proposed design has been simulated using Cadence tools, and a prototype has been manufactured in a 0.18-$\mu $m CMOS process. The fabricated prototype consumes an effective silicon area of$37.2\times 10^{3}~\mu $m2and can sustain a breakdown voltage of 710 Vrms. Experimental results show that the proposed solution achieves a CMT immunity (CMTI) of 2.5 kV/$\mu $s at a data rate of 480 Mb/s with a BER of$10^{-12}$. The propagation delay is 3.9ns with a 4 ps/°C variation rate over temperatures ranging from$- 31~^{\circ }$C to$100~^{\circ }$C. Under typical test conditions, the BER reaches$10^{-15}$with a peak-to-peak data dependent jitter (DDJ) of 29.8ps.