N-Bit ALU Design Using Vedic Mathematics
M. V. Ramakrishna · INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT · 2025
Abstract - The Arithmetic and Logic Unit (ALU) is a central component in modern computing systems, responsible for performing core arithmetic and logical operations. This paper proposes an N-bit ALU designed using Vedic mathematical principles to achieve improved speed and reduced power consumption. Leveraging the Urdhva Tiryakbhyam principle from Vedic mathematics, the ALU integrates an efficient multiplier along with high-performance arithmetic and logic units. The architecture, developed using Verilog HDL and synthesized through Xilinx Vivado, exhibits lower delay and efficient hardware usage, making it well-suited for applications in embedded systems and signal processing. Key Words: Vedic Mathematics, N-Bit ALU, Urdhva Tiryakbhyam Algorithm, Verilog HDL Implementation, High-Speed Multiplication, FPGA Synthesis