Obstacle Avoidance in Routing with GNR Interconnect
Subrata Das, Arighna Deb, Soumya Pandit, Debesh Kumar Das · 2025
During the routing phase of VLSI physical design, obstacles often arise along the routing paths due to previously established connections or other constraints. These obstacles pose significant challenges for VLSI designers in constructing efficient routing trees that navigate around them. Graphene nanoribbon interconnects, which are limited to bending angles of 0°, 60°, and 120°, further complicate this process. The routing cost for graphene nanoribbon interconnects depends on both the interconnect length and the bending angles involved. In this work, we propose a cost-minimization technique that leverages graphene nanoribbon interconnects to determine optimal routing paths for a given source node, a set of sink terminals, and multiple rectangular obstacles.