Design of Low-Latency, Area- and Power-Efficient CORDIC Algorithms for Sine/Cosine Floating-Point Computation
Prashant Sharma, Sourav Nath, Koushik Guha, Krishna Lal Baishnab · 2025
This article proposed a system that uses the CORDIC algorithm to compute the sine and cosine functions of floating-point parameters in an area and power-efficient manner. In order to maximize hardware area, power consumption, and memory utilization while maintaining high computational accuracy, the proposed method uses approximation adders rather than conventional ripple carry adders. The novelity of this work is the design of a low-latency system and the reduction of area and power consumption. Which is accomplished through architectural optimizations including using DSP blocks in FPGA for improved performance and reducing the amount of memory used for precomputed angles. Compared to the traditional ripple carry adder implementation, which uses 1.78 mW and has a delay of 1.037 ns, the proposed CORDIC design consumes 1.67 mW, has a latency of 0.427 ns, and reduces the cell area by about 8.15%. With an accuracy of 99.967%, this work offers a major breakthrough in CORDIC optimization for embedded systems, especially for applications involving digital signal processing (DSP) and image processing. Performance research indicates that the proposed design offers advantages in hardware area use and power economy while striking a balance between accuracy and performance.