Lightweight 64-bit AES-Inspired Symmetric Cryptographic Core for Low-Power and Resource-Constrained Systems
Subha Bhattacharya, Aakash Bose, Divyansh Dutta, Anirban Das, Shirshak Chakraborty, Sayan Chatterjee · 2025
The paper presents the design of a lightweight, high-speed and low-power symmetric cryptographic core inspired by the Advanced Encryption Standard (AES) for resource-constrained environments like IoT applications and embedded systems. The proposed architecture retains AES principles while optimizing for minimal resource utilization by reducing block and key sizes to 64 bits. The design is implemented using SystemVerilog, synthesized and simulated on Xilinx Kintex-7 (xc7k70t-fbv676) FPGA to evaluate performance metrics. The simulation results verify the correctness of encryption and decryption operations, and timing analysis indicates encryption and decryption latencies of 70 ns and 75 ns, respectively. The core runs at an optimized frequency of 228.65 MHz and processes at a throughput of 248.02 Mbps, which is appropriate for real-time secure communication. The low hardware footprint, optimized combinational logic, and minimal switching activity contribute to significantly reduced dynamic power consumption, making this cryptographic core a low-power alternative for security applications.