Energy-Efficient 4-Bit Multiplier for High Performance and Low Power Consumption
Amrita Chakrabarty, Subhash C. Bhattacharya, Nabamita Bakshi, Sayan Chatterjee · 2025
Power-efficient multiplier design plays a critical role for enhancing energy efficiency and performance in modern digital systems. This study presents an optimized 4-bit array multiplier using CMOS technology (GPDK 90nm) and a Transmission Gate (TG)-based approach. The design integrates TG-based AND and XOR gates with an enhanced full-adder circuit, ensuring improved signal integrity, reduced power dissipation, and lower propagation delay. Simulations in Cadence Virtuoso show a 61.49% reduction in power dissipation and a 70.97% decrease in delay compared to conventional designs. These results highlight the proposed multiplier's potential as a low-power, high-performance solution for VLSI applications.