Design And Implementation Of Power Efficient Multiplier Using Reversible Logic
K. Yashoda, K V Gowreesrinivas, M. Mahesh, K S V L D Sai Phanindra, Aman Syed, S. Nayana Sai · 2025
In current VLSI Technology, Power Consumption has emerged as a very significant factor to consideration. The primary goal of this project is to design various bits of multiplier using reversible logic circuit with low Power Consumption. Here Power consumption is based on minimum Quantum cost. Lower the Quantum cost lower the Power Consumption. When designing reversible logic algorithms for multipliers, power consumption can be greatly optimized compared to conventional logic-based circuits. Reversible logic is defined by having an equal number of output lines and input lines. Reversible logic includes the use of reversible gates. There are several reversible logic gates, including the Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, and Toffoli Gate. A comparative study is also given, considering garbage outputs, quantum cost, and the number of gates. Reversible logic is applied in embedded systems where power efficiency is important. In this Project, various bits of multipliers are designed using reversible logic. These circuits are optimized to have minimum quantum cost and produce the least number of garbage outputs.