Floating Point Multipliers on FPGAs
U. S. Singh, Rahul Mundliya, Raushan Maharana, Babita Jajodia · 2025
This work presents IEEE 754 compliant floatingpoint multipliers for various formats: Half Precision (HP), Single Precision (SP), Double Precision (DP), Double Extended Precision (DEP), and Quadruple Precision (QP), with bit lengths of 16, 32, 64, 80, and 128 bits, respectively, implemented on Field Programmable Gate Arrays (FPGAs). The study explores different mantissa multipliers – Optimized Schoolbook Multiplier (OBSM), Hybrid Karatsuba Multiplier (HKM) and Hybrid Recursive Karatsuba Multiplier (HRKM) – to identify the most efficient mantissa multipliers that comply with the IEEE 754 standard and are suitable for floating-point multipliers. Hardware implementations show that the proposed HRKM-based SP and DP floating-point multipliers show a better Area-Time-Product (ATP) performance of 79. 599% and 83. 901%, respectively, in comparison to the latest state-of-the-art work on the AMD Kintex Ultrascale KCU105 FPGA platform.