Simulador Interativo para Programação na Arquitetura de Processadores RISC-V
Eduardo Michel Deves de Souza, Larissa De Sousa Gouvea, Cesar Albenes Zeferino, Douglas Rossi de Melo · Anais do Computer on the Beach · 2025
The RISC-V architecture, recognized for its modularity and efficiency,faces challenges due to the limited availability of educationalresources. To address this issue, an interactive web simulator wasdeveloped based on the RV32I instruction set, using the Angularframework, with an interface integrated into a core comprising acode parser, assembler, and processor, enabling both continuousand step-by-step execution. The simulator’s validation confirmedthe proper functioning of essential features, including code editing,assembling, execution, and visualization of registers and memory.This simulator is intended for students, educators, and embeddedsystems designers in projects involving the RISC-V architecture,serving as a teaching tool in computer architecture courses.