An energy efficient two-stage dynamic comparator using cascode configured pre-amplifier and common drain latch scheme with low kickback
Vikas Tiwari, R. K. Nagaria · Engineering Research Express · 2025
Abstract This study proposes a double-stage dynamic comparator for low-power VLSI and biomedical applications. Combining the suggested common drain-based latch and cascode-configured pre-amplifier stage has the advantage of low kickback noise with less power dissipation. The proposed dynamic comparator’s overall delay is decreased compared to other recently reported dynamic comparators because the latch stage’s charging and discharging times are shortened, lowering the power delay product (PDP). An input differential voltage (ΔV in ) of 5 mV and a common mode voltage (V CM ) of 0.9 V result in an average power dissipation of 12.33 μW and a delay of 65.21 ps. 1- σ offset voltage is 7.07 mV, and the σ -kickback noise is 0.53 mV for the 1 V supply voltage at 250 MHz clock frequency and 5 mV of ΔV in . The proposed comparator circuit operates at a supply voltage of 1 V and a clock frequency of 250 MHz, making it suitable for medium-speed SAR ADC applications.