Static Communication Analysis for Hardware Design
Mads Rosendahl, Maja H. Kirkeby · Electronic Proceedings in Theoretical Computer Science · 2025
Hardware acceleration of algorithms is an effective method for improving performance in highdemand computational tasks.However, developing hardware designs for such acceleration fundamentally differs from software development, as it requires a deep understanding of the highly parallel nature of the hardware architecture.In this paper, we present a framework for the static analysis of communication within datapath architectures designed for field-programmable gate arrays (FPGAs).Our framework aims to enhance hardware design and optimization by providing insights into communication patterns within the architecture, which are essential for ensuring efficient data handling.