Optimized Low-Power FIR Filter Design Using Residue Number System for Energy-Efficient DSP Applications
Cheruku Navaneeth Kumar Goud, C. S. Kavya, S. Bharath, J. V. R. Ravindra · 2025
In modern digital signal processing (DSP) systems, power efficiency is a critical design consideration, especially for portable and battery-powered devices. This project presents an optimized low-power FIR (Finite Impulse Response) filter design using the Residue Number System (RNS) to achieve energy-efficient DSP applications. Traditional FIR filters, while effective, are often power-intensive due to the high computational complexity involved. The RNS offers a promising alternative by enabling parallelism and reducing the size of arithmetic operations, leading to lower power consumption without sacrificing performance. In this project, we explore the integration of RNS with FIR filter architecture, focusing on optimizing modular arithmetic operations to reduce power consumption while maintaining high throughput and precision. The design methodology includes theoretical analysis, hardware implementation, and performance evaluation, demonstrating the advantages of using RNS in reducing both dynamic and static power in DSP systems. Experimental results showcase significant power savings compared to conventional FIR filter designs, making this approach highly suitable for next-generation DSP applications in mobile, wireless communication, and IoT devices.