An Adaptive PWM Scheme for Fast Ramp-Up DC-DC Boost Converters in SSD Applications
Yuji Kanayama, Tôru Tanzawa · 2025
This paper investigates pulse-width modulation (PWM) for switching boost converters to achieve the fastest ramp-up when generating programming voltages for NAND Flash in solid-state drive (SSD) applications. The PWM must be designed under conditions where the capacitive load (CL) of the boost converters varies depending on the number of NAND dies selected for simultaneous programming, and the rated inductor current (IR) varies depending on the inductor used in the boost converter. The ramp-up time is estimated using models for four PWM schemes: 1) maximizing output current at any output voltage (IO max), 2) maintaining the inductor current at IR (IR limit), 3) using a constant duty ratio (Const.D), and 4) operating in boundary current mode (BCM). An interesting result was that each of the four extreme cases, in terms of CL and IR, had a different optimal PWM scheme. The model results are compared with SPICE simulations and measured results using 24 V transistors in a 250 nm CMOS. To minimize ramp-up time across a wide range of load capacitances, an adaptive PWL scheme is proposed that selects one of two or three PWM schemes depending on the number of NAND chips being programmed simultaneously.