SimGen: Simulation Pattern Generation for Efficient Equivalence Checking
Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipović · 2025
Combinational equivalence checking for hardware design tends to be slow due to the number and complexity of in-termediate node equivalences considered by the SAT solver. This is because the solver often spends extensive time disproving nodes that appear equivalent under random simulation. We propose SimGen, an open-source and expressive simulation pattern generator inspired by Automatic Test Pattern Generation (ATPG); it exploits the circuit's structure to disprove the equivalence of circuit nodes and avoid excessive SAT calls. We demonstrate the effectiveness of SimGen's simulation patterns over those generated by state-of-the-art random and guided simulation.