Power Estimation of Radix-2 and High Radix Embedded Divider IP Core 5.1 for FPGAs Using Regression Technique
Harshita Prasad, Ashwni Kumar · Journal of Circuits Systems and Computers · 2025
The Field Programmable Gate Arrays are gaining popularity nowadays due to their complex reconfigurable architectures. These complex architectures help designers to implement computationally intensive design applications related to signal processing, communication, image processing etc. In order to reduce the design turnaround time, it is preferred to utilize the off-shelf components i.e., Intellectual Property (IP cores). Embedded blocks that are accessible in IP cores can be called in design according to the design applications using the Vivado repository. One of the fundamental IP cores is the divider. This IP core can be configured for Radix-2 and High Radix configuration that trade-offs among the resources used, throughput, and latency. But there is no power and area estimate for these combinations that are given in the datasheet or in the literature. As a result, this work uses early power and area estimate model based on Xilinx Zynq SOC for Radix-2 and High Radix divider generation IP core 5.1 intended for Zed Board. Supervised machine learning has been used to create the models. i.e., curve fitting and regression with the IP core tool of the Vivado design suite, different I/O vector length division generator setups are created. To estimate the area and power, the proposed models have been utilized and Vivado Power Estimation/Synthesis Tool used for validation. The power models have an average error of 0.28 and 0.25% for Radix-2 and High Radix respectively, indicating their good accuracy respectively. However, the Radix-2 area models are providing an average error of 0.06 and 0 for LUT and Flip-flop estimation, respectively. Similarly, the High Radix area models are providing an average error of 3.1, 1.6 and 1.9 for LUT, Flip-flop and DSP48 estimations, respectively.