Design of reconfigurable and parameterizable generic sequence detector
P.B. Nandhu Krishna, Ramesh Bhakthavatchalu, R S Geethu, K.R. Jayakrishnan · 2025
This paper presents the implementation of a reconfigurable and parameterizable N-bit sequence detector which can detect any given pattern in the incoming stream of bits. The design is having a generic code, capable of recognizing any sequence, regardless of its length, and accommodating both overlapping and non-overlapping sequences. Designed to function on a shift register architecture instead of a state machine architecture, it offers advantages over conventional FSM based systems with greater reconfigurability. This also cuts down the design time and provides a flexible solution for sequence detection requirements. A reconfigurable and parameterizable generic sequence detector is designed using Verilog and analyzed in Vivado Design Suite for FPGA implementation.