Design and UVM-Based Verification of unified AXI4 and AXI4-Stream Protocols
K R. Mohanakrishnan, R. Saravana Kumar · 2025
System-On-Chip (SoC) designs increasingly rely on both memory-mapped AXI4 and high-throughput AXI4-Stream interfaces to handle diverse data transactions. However, verifying these protocols in isolation often leads to missed corner cases and integration issues. This paper presents a unified, coverage-driven UVM testbench that validates AXI4 and AXI4-Stream within a single, reusable environment. By combining modular agents, constrained-random stimulus, and an integrated scoreboard, we achieve robust concurrency testing and comprehensive protocol checks. Crucially, our coverage analysis, incorporating detailed coverage points for individual signals and their cross-combinations, achieved 100% coverage. This indicates we effectively tested every targeted scenario— from typical burst transactions to edge cases involving packet transfers. Achieving full coverage ensures strong confidence in protocol correctness and greatly reduces the effort needed to detect and resolve subtle, corner-case bugs.