Low Power Hybrid Full Adder Design using MGDI Based XNOR Gate with Swing Restored Technique
Ujala, Manoj Kumar · 2025
Low power becomes more and more necessary as technology advances. One of the essential parts of the arithmetic logic unit is the full adder that determines the performance of the arithmetic logic unit. Many authors have proposed a modified structure and novel technique for the full adder cell to achieve high performance. In this work, we have proposed the modified full adder cell with the swing-restored technique to minimize power consumption. A comparative analysis of the full adders has been performed by Cadence Virtuoso with 90nm and 45nm technology in terms of delay, power, and PDP. The reduction in power consumption of modified full adder with respect to conventional adder is 29.11 % and with respect to 22T full adder, it is 24.61%.