Performance Optimization of FIR Filters Using Approximate Multipliers
Aluvoju Vivek, Arun Sekar Rajasekaran, MD Badhesha · 2025
Area, Power, and Delay is the fundamental triangular loop on which complete Very Large Scale Integration(VLSI) depends. Achieving a trade-off among these three parameters is a bit challenging. However, approximate computing makes this possible by compromising accuracy at the output, which is acceptable in multimedia applications. Inspired by this, the approximate design of Full Adder, Compressor, and 4x4, 8x8 Vedic Multipliers used in building an FIR low pass filter is proposed to optimize its performance. Those circuit designs are comparatively evaluated with parameters such as area, power, delay, and Power Delay Product in Digital Cadence. Not only the parametric evaluation but also evaluation is done with image addition as an image processing application. Further, the processed image is evaluated with Structural Similarity Index Measure, Peak Signal-To-Noise Ratio, Mean Squared Error, and Mean Absolute Error to validate the proposed method. This metrics evaluation is done using Python code.