A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET
Prashanth Mohan, Siddharth Das, Ken Mai · 2025
Edge computing devices are often tasked with a diverse array of workloads including signal processing, cryptography, and machine learning. These devices must balance escalating computational demands with stringent power constraints, often relying on fixed-function accelerators to meet these requirements. However, the inherent inflexibility of these hardened accelerators poses a significant limitation, as the algorithms and requirements can change throughout the device lifecycle. Designers have investigated various approaches to enhance flexibility while retaining high throughput and energy efficiency. Extending the ISA of open architectures like RISC-V with custom instructions has shown promise [1]–[4], though selecting and evaluating the optimal set of extensions remains challenging. An alternative is integrating an embedded Field Programmable Gate Array (eFPGA) on the SoC as a loosely coupled programmable accelerator [5]–[9], enabling enhanced throughput, energy efficiency, and adaptability. However, prior works rely on generic eFPGAs hard-IP [5], [8], [9] with pre-defined architectures, often lacking sufficient resources to handle compute-heavy workloads, resulting in poor energy efficiency and high area overheads. In this paper, we demonstrate a combination of the two approaches by tightly coupling an eFPGA to the RISC-V CPU and SoC memory while tailoring the eFPGA architecture for compute-heavy workloads to improve the throughput and energy efficiency by 1–2 orders of magnitude over the RISC-V CPU.