Demonstration of Logic-Block Performance-Power-Area Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node
Hidenobu Fukutome, J. Kim, Jae‐Sun Shin, J. Kim, Y. Lee, S. Chae, B. Eom, Yunhun Nam, M. Lee, Sanghyun Ha, E.G. Chung, S. H. Lee, S. Kim, Keun Hwi Cho, K.W. Lee, Dongwook Kim, H.-J. Cho, K. Rim, J. Song · 2025
Since both parallel computing and multi-application expected for advanced System-on-Chip (SoC) and High-Performance-Computing (HPC) use a lot of transistors with a high performance and low power consumption, continuous scaling has been required for not only transistor but also standard cell as done until 3 nm technology node [1], [2]. For example, vertical scaling of the standard cell has been done by reducing either width of transistor active regions or space among them. Recently, back-side power delivery network (BSPDN) is considered to be another option to decrease the standard cell size [3], [4] and its usefulness has been demonstrated [4]–[6]. One of the merits to implement BSPDN is expected by simulation [7] to be reduction of IR-drop which enhances the cell performance in block level. As schematically illustrated in figure 1(a), front-side power delivery network (FSPDN) occupies significant area in Cu interconnect multi-layers and supply voltage must be applied from the top layer through many wires and via to power rail in the bottom layer. In contrast, not only supply voltage is simply applied from back-side (BS) interconnect without complicated path but also routing space is generated in front-side (FS) interconnect after removing FSPDN from the FS, as show in Fig. 1(b). Such effect is expected to be significant especially in HPC application due to the density higher than SoC one [8]. Figure 2 show schematic illustrations of BSPDN options published in reports [9]. In early version of BSPDN, BS interconnects under the devices would provide power to FS Cu interconnects as shown in Fig. 2(b) [3], [7], [12]. In particular, FS and BS Cu layers are simply connected in power tap cell (PTC) without buried power rail. A merit to use PTC is to be possible to maintain the baseline of fabrication process in transistors and contacts optimized for scaled contacted poly pitch$(\mathrm{C}_{\text{pp}})$used in devices with FSPDN shown in Fig. 2(a). Of course, since small PTC (sPTC), which is used in our$1^{\text{st}}$generation (Gen) BSPDN, required for scaled$\mathrm{C}_{\text{pp}}$and standard cell height (CH) must be shrunk with keeping low resistance, vertical scaling of sPTC has been done by aggressively thinning Si substrate. On the other hand, since keep-out zone for sPTC has to be avoided in order to increase the number of available transistors, layout effects induced by sPTC should be suppressed. Even although power rail must be remained in FS Cu interconnect, gain of performance-power in block level had been expected with BSPDN featuring sPTC [9]. In contrast, in the case of option which BS Cu layer is connected with FS contact metal shown in Fig. 2(c) [4], [5], [9], [10], since it is not necessary to maintain power rail in FS Cu interconnects, it is possible to optimize FS Cu layers suitable for signal wiring. Moreover, since source electrode of the devices would be directly connected with BS interconnects in advanced one [6, 9–11] as shown in Fig. 2(d), further CH scaling would be expected by removing space where there had been power delivery via from BS interconnect. Therefore, either scaling or removing power rail in FS results in vertical scaling of the standard cell. Effect of each option of BSPDN on transistor characteristics has experimentally reported [4], [6], [10], [12] and its usefulness had been verified by block level gain with a FinFET technology [5]. Then, whereas such BSPDN would be applied on gate-all-around (GAA) FET technology beyond 2 nm node, there was no report of experimental research for BSPDN impacts on block level performance-power-area (PPA) in such technology. In this study, we have experimentally demonstrated effects of BSPDN on standard cell performance scaled down for SoC and HPC technology featuring GAA FETs beyond 2 nm node [13]. Moreover, we have achieved to overcome side effects potentially concerned for technologies with BSPDN featuring sPTC. Then, we have experimentally clarified feasibility of further CH scaling with keeping speed and leakage current for the first time.