An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface
Giyeong Heo, Younghwan Chang, Yong-Un Jeong, Jaekwang Yun, Jusung Lee, Shin-Hyun Jeong, Sanghyuk Seo, Suhwan Kim · 2025
To meet the demand for high bandwidth memory, PAM-4 signaling has been recently introduced as an alternative to conventional NRZ signaling [1]–[5]. Although achieving twice the per-pin data rate of NRZ at the same clock frequency, PAM-4 signals are more vulnerable to noise sources such as inter-symbol interference (ISI), crosstalk (XT), and power noise due to a reduction in vertical and horizontal eye margin [2], [3]. To mitigate these noise sources with minimal area, PAM-4 data coding schemes have been proposed [1]–[5]. Most of these works use lookup table (LUT)-based 7b/8b maximum transition avoidance (MTA) coding to improve the signal integrity (SI) by eliminating maximum transitions, which significantly degrade both ISI and XT [1]–[4]. For 7b/8b MTA coding, the extra pin formerly used for data bus inversion (DBI) is used to transfer 1-bit of unencoded data per lane to maintain data bandwidth as before encoding. However, due to the absence of the DBI function that was originally used to improve energy efficiency and supply voltage fluctuation [6], power noise has become more critical in the 7b/8b MTA. In addition, applying DBI in conjunction with MTA using an extra pin is not a viable solution since it can regenerate maximum transitions [3]. Therefore, additional compensation circuits such as low-dropout (LDO) regulators is used to minimize power noise, but at the cost of additional area and power overhead [1].