Physical Design (RTL-GDSII) Implementation of State Transition Graph-Based Sequential Multiplier
Satyanarayan Padhy, L. Mounika, Palavalasa Manikanta Varaprasad, Yernagula Roshit · 2024
The State Transition Graph (STG) Multiplier is a high-performance digital circuit architecture designed to efficiently handle large-scale multiplication operations by leveraging state transitions for optimized computation flow. This design approach systematically reduces the number of state transitions in generating partial products, thus minimizing the critical path delay and overall power consumption and area. The paper presents a sequential multiplier's physical design (RTL-GDS) using a state transition graph (STG) controller. The physical design of the STG Multiplier across three different technology nodes, 45nm, 90nm, and 180nm, has been implemented and compared with the existing multipliers to validate that the proposed STG multiplier is more efficient. Performance metrics, including area, delay, and power, have been meticulously calculated using the Cadence EDA tool. This study underscores the advantages of the STG approach in enhancing area, timing performance, optimizing speed, reducing power consumption, and improving interconnect complexity.