Power, area, and delay efficient synchronous ring counter using clock gating and multi-bit flip-flops in QCA technology
A. Arunkumar Gudivada, Gummarekula Sattibabu, Anil Kumar Relangi · International Journal of Electronics Letters · 2025
Optimizing power, area, and delay is crucial for efficient digital designs. This paper presents a QCA-based Ring counter integrating Clock Gating (CG) and Multi-Bit Flip-Flops (MBFF) to enhance performance. QCA technology offers a compact, low-power alternative to CMOS. CG reduces power by selectively enabling the clock, while MBFF optimises area by minimising sequential elements. The proposed design achieves 0.082 nW power consumption, 0.28 μm2 area, and 20 ps delay using 979 quantum cells. Compared to conventional designs, it improves cell count, area, delay, and power by 18.73%, 6.66%, 33.33%, and 83.6%, respectively. These results confirm the efficiency of the QCA-based Ring counter with CG and MBFF for high-speed, low-power nanotechnology applications.