A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM
Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Eun-Bi Koh, Joo‐Hyung Chae · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
Recently, the demand for supporting diverse artificial intelligence (AI) operations within a single edge device has been increasing. However, existing compute-in-memory (CIM) architectures for edge AI are often optimized only for specific lightweight networks, limiting their adaptability. While digital CIM (DCIM) offers high accuracy and exhibits low sensitivity to variations in process, voltage, and temperature, their area and energy inefficiencies remain significant barriers to deployment in edge devices. This study proposes an embedded dynamic random access memory (eDRAM)-based dual-multiplication-mode (DMM) DCIM macro leveraging precharge-controlled 4T1C gain cells. The proposed design enables the AND/XNOR dual-multiplication mode within a 4T1C cell through controlled precharge states. It supports a wide range of neural networks for edge AI, including INT1–8 operations and binary neural networks, such as XNOR-net. An area-efficient adder tree structure reduced the transistor count by 19% compared to conventional adder trees. This structure also accommodates 1–8-bit signed and unsigned inputs and weights without wasting cells, enhancing reconfigurability. Fabricated using a 28-nm CMOS process, the 16-kb DMM-DCIM prototype chip demonstrated area and energy efficiencies of 28.9 TOPS/mm2and 190.3 TOPS/W for 4b–4b multiply-accumulate operations, respectively.