FPGA design of an efficient divide-and-conquer multiplier based on multiple stage fast ripple hybrid adders for peak cancellation with IIR filters
K. Bala Sindhuri, Sarala Patchala, Koteswari Surapaneni, Madam Aravind kumar, G. Challa Ram, Prabhakar Rao Desamala · International Journal of Electronics · 2025
The evolution of Digital Signal Processing (DSP) systems within Very Large Scale Integration (VLSI) era has significantly impacted computational speed, chip size, and power consumption, consequently influencing the overall cost of systems. Typically, sophisticated DSP systems, including peak cancellation with infinite impulse response (PC-IIR) filters, require multiple arithmetic units. Therefore, the performance of PC-IIR filters can be significantly improved by efficient design of arithmetic logic circuits. In this paper, a new multiple-stage fast ripple hybrid adder (MS-FRHA) and Compressor-based divide-and-conquer vector multiplier (CDCVM) is introduced for PC-IIR filter. Multiple single-stage carry select structures are combined in the proposed MS-FRHA to increase area, delay, and power performance. Also, CDCVM effectively handles huge numbers by dividing the multiplication problem into smaller sub-problems and uses compressor-based Vedic multiplication (CVM) for each sub-problem. According to simulation data, the proposed arithmetic logic circuits use the least amount of space, time, and power of all the earlier designs. Furthermore, a comparison to the most advanced PC-IIR filter shows that the proposed model can reduce delays and resource consumption.