Modeling Xilinx Ultrascale FPGA Fabric with FABulous
Renju Rajeev · 2024
This study explores the feasibility of implementing a modern FPGA fabric using the open-source tool FABulous, focusing on the Xilinx Ultrascale architecture as a case study. FPGAs have emerged as versatile integration mediums for digital designs, offering reconfigurability and reduced time-to-market compared to conventional ASICs. Despite historical challenges in FPGA development due to closed-source environments, recent advancements in open-source CAD tools have enabled greater accessibility and affordability in FPGA design. Leveraging tools like FABulous, which allows the modeling of FPGA fabrics using CSV description files, designers can create FPGA devices from within an Excel spreadsheet. This research delves into the methodology of extracting architecture information from Xilinx tools and transforming it into a model usable by FABulous. The study also includes the implementation details and comparative analysis with existing FPGA fabrics. Through this work, I demonstrate that FABulous can effectively model and implement complex FPGA fabrics, paving the way for broader accessibility and innovation in FPGA design.