SecureX: Strategically Securing Designs Against Oracle-Less Attacks Using GNN-Based Explainers
Likhitha Mankali, Ozgur Sinanoglu, Satwik Patnaik · IEEE Transactions on Circuits and Systems I Regular Papers · 2025
Logic locking is a promising design-for-trust solution that protects integrated circuits (ICs) from hardware security threats such as design intellectual property (IP) piracy and illegal overproduction of ICs. With the ubiquity of machine learning (ML), researchers have proposed various ML-based attacks against logic locking techniques in recent years. Since ML-based attacks operate as non-interpretable models, understanding the reasons behind the success/failure of such attacks is challenging. In this work, we propose SecureX, the first-of-its-kind technique that employs an explainable Graph Neural Network (GNN) to lock designs. The unique benefits of explainable GNN-based analysis include identifying the best locations in the design to lock, and the critical features (structural/functional) that make the designs vulnerable to ML-based attacks. Moreover, SecureX seamlessly integrates with state-of-the-art unbroken scan-chain protection techniques, thus thwarting oracle-guided attacks. We perform experiments on ITC-99 benchmarks and two types of locking techniques (X(N)OR/MUX-based locking) to demonstrate the efficacy of SecureX in locking designs resilient to ML/non-ML-based attacks. Our results confirm that the accuracy of the state-of-the-art ML/non-ML-based attacks drops to ≈50% while maintaining low area/power/delay overheads. Moreover, we perform a practical case study of locking an image-processing application.