Approximate Full-Adder, Full-Subtractor, and Full-Adder/Subtractor Circuits Based on QCA
Saeid Seyedi, Hatam Abdoli · 2025
QCA has garnered a lot of attention lately because to its promise for low latency, compact space, low complexity, and low power consumption. At the same time, a new nanotechnology paradigm called approximation computing simplifies computation high-performance design method, and becomes a low-power for calculation circuits. Additionally, a lot of digital circuit design has made use of the XOR gate. A crucial part of QCA technology, the full-adder (FA) circuit is used for arithmetic logic unit operations such as subtraction, multiplication, and division. The design of approximation FA, full-subtractor (FS), and full-adder/subtractor (F$A$/S) has been extensively studied. The approximate F$A$/S designs demonstrated just 10 cells utilized in implementation, an area of 0.01μm2, and a delay of 0.5 clock phases. Specifically, the approximate FA and FS designs achieved an area of 0.01 μm2and a latency of 0.5 clock phases. By using the QCADesigner tool for functional verification, the efficacy of these designs was confirmed. Three new and innovative QCA-based circuits-FA/S, FS, and FA approximations-are presented in this work. Accessing the components without being surrounded by other cells is made easy by the fact that each design has outputs on one side and the inputs on the other side.