Design and Performance Analysis of Hybrid VCMA + STT-MTJ/CMOS Circuits for CIM Architecture
Prashanth Barla · IEEE Transactions on Magnetics · 2025
Emerging computation-in-memory (CIM) architecture effectively overcomes the limitations such as memory wall and rise in standby power dissipation associated with conventional von-Neumann structure. In this article, we developed hybrid voltage controlled magnetic anisotropy assisted spin transfer torque magnetic tunnel junction (VCMA+STT MTJ) circuits for the CIM architecture. Initially, we have proposed a novel VCMA+STT MTJ write circuit that is 63.35% and 94.86% more energy efficient with 50.87% and 59.42% lower transistors compared to spin-Hall effect assisted (SHE) assisted STT and STT MTJs respectively. Subsequently, development of VCMA+STT non-volatile full adder (NVFA) with the novel write circuit unravels its supremacy with 42.21% and 89.25% reduction in total power dissipation, 35.16% and 41% lower transistor count, 31.93% and 95.13% faster write speed, and 62.79% and 99.53% lesser write power delay product (PDP) compared to SHE+STT-NVFA and STT-NVFA respectively. Using VCMA+STT-NVFA, we have developed a NV-arithmetic logic unit (ALU) to perform addition, subtraction, and all the logic operations. Comparison of the same has been conducted with its CMOS counterpart to show that NV-ALU is better in terms of power dissipation, and transistor count by 12.12%, and 15.71% respectively. Furthermore we have extended the NV-ALU for 4-bit operations to show its feasibility for higher-bit operations.