Novel Approach of Digit Serial Multiple Constant Multiplication in DSP Applications
Rajendra M. Rewatkar, Chetan Puri, Amit Anil Gudadhe, Shubhangi V. Rathakanthiwar, Nitin J. Wange · 2024
Paper Presents optimization technique for adder, multiplier and FIR filter using different architectures. Most important part of a DSP processor is the multiplier and accumulator. Multiplication is a heavy weighted process in computation and hardware, whereas adder is a light weight but important unit in any processor which basically leads to a number of operations like addition, subtraction, increment, decrements etc. Digit-serial operation is best suited for execution of DSP systems which need moderate sampling rates. This digit serial architecture allows bit-level pipelining, thus realizing sample speeds corresponding to bit-parallel multipliers showing less area. Paper presented a novel approach of digit-serial multiplier styles with MCM. In this research, the valuation of complex pathway and power dissipation of different digit serial multipliers besides their deviation at various digit sizes is discovered. At last, FIR Filter with Digit Serial Architecture along with MCM is designed through Active-HDL and Xilinx The results for power, area and speed are tested and a report is included. Attention has been given to the digit serial design which offers alternate low complication in processes. Investigational observations have exposed the effectiveness of the projected method and the circuit of digit serial methods causes low power consumption of FIR filters. Digit serial techniques with MCM improve the essential parameters in DSP implementation.