High Throughput-to-Area AES: The Role of Small S-Box in Lightweight Cryptographic Design
Yuri Silva Vaz, Júlio C. B. Mattos, Rafael Iankowski Soares · 2025
Data security is an essential prerequisite for the effective functioning of modern systems. It guarantees the secure transmission of information to thwart unauthorized access and potential data breaches. Cryptography plays an indispensable role in safeguarding sensitive data during communication. The Advanced Encryption Standard (AES) is an esteemed choice among symmetric key algorithms, owing to its proven reliability and robust security features. Despite its extensive adoption, optimizing AES implementations to achieve high throughput while minimizing hardware resource consumption, particularly in area, is a significant challenge. This study addresses the challenge of reducing area usage while enhancing the throughput of the algorithm by focusing on improving the throughput-to-area efficiency of AES through a novel hardware implementation. This approach introduces an optimized SubBytes stage featuring a smaller S-box comprising just 16 elements. The proposed optimization enables an enhanced throughput per area (Mbpslk-gate), providing a more balanced solution for lightweight en-cryption applications. It allowed a notable area reduction of 84%, alongside doubling the maximum frequency compared to the original implementation. In terms of throughput-to-area efficiency, the optimizations resulted in a value 12.5 times greater than the original design's. Furthermore, the security robustness of the modified algorithm is confirmed through three distinct security tests, validating its reliability and suitability for practical deployment.