Evaluation of Transient Fault Tolerance in Different Logic Styles of 2: 1 Multiplexers
Reis Ana Flávia D., Sandoval Bernardo B., Cristina Meinhardt, Werhli Adriano V., Rafael B. Schvittz · 2025
As CMOS technology dimensions continue to reduce, radiation-induced reliability challenges are becoming increasingly prominent. Effective strategies to mitigate radiation-induced soft errors are critical for maintaining the reliability and performance of advanced technology nodes, showing that the choice of a logic style is essential, which may directly influences circuit robustness. This work aims to analyze the robustness of different 2:1 multiplexer designs to transient faults using static logic styles. Electrical simulations were performed with 32nm High-Performance technology, and Linear Energy Transfer values were assessed through P-hit and N-hit fault effects. Results show that CMOS and DCVSL logic styles exhibit strong performance in terms of robustness to radiation.