SR-latch Based Ternary Content Addressable Memory with Reduced Delay
S Shanthini, M S Sunita · 2024
This work deals with the implementation and analysis of Ternary Content Addressable Memory array constructed with OR-AND-Invert SR latches. A pair of differential bit cells consisting of these latches is connected to an AND-OR-Invert based multiplexer. During search operation, selective mapping is performed by the MUX to determine match result across the match line. Multiple bit cells are combined to create a bit-slice. These bit-slices are arranged to form the array. The proposed design is simulated in 45nm CMOS technology. A 4×16 TCAM array is implemented with parallel matching technique operating at 1GHz with a reduced delay by 11% when compared to the existing work. An average power consumption of 1.81mW and overall energy consumption of 4.087pJ is observed. Process corner analysis for match line delay with worst-case and best-case mismatch for search operation has also been performed for all the corners.