Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level
Behnam Farnaghinejad, Antonio Porsia, Annachiara Ruospo, Alessandro Savino, Stefano Di Carlo, Ernesto Sánchez · 2025
Leakage assessment at the Register Transfer Level (RTL) is essential for identifying vulnerabilities in various designs, including cryptographic systems, AI models, and other applications handling sensitive data during the design phase. This paper introduces VeriSide, an innovative framework built as a modified version of Verilator to generate compact format files that directly capture side-oriented information, such as Hamming Distance (HD) or Hamming Weight (HW) of the signals. VeriSide streamlines the power side-channel (PSC) analysis process by providing efficient and scalable solutions for large-scale designs. Traditional methods relying on verbose Value Change Dump (VCD) or Switching Activity Interchange Format (SAIF) files face significant scalability and resource challenges, especially for complex systems-on-chip (SoCs). These methods incur substantial storage and processing overheads. VeriSide overcomes these limitations by drastically reducing file size and eliminating post-simulation memory usage, while maintaining analysis accuracy.