Low-Area-Cost VLSI Architecture of Fault-Aware High-Reliability Triple-Mode Polar Decoder Chip Reconfiguring SC and SCL Decoding
Xin-Yu Shih, D.M. Wu, Wei-Lun Chang · IEEE Transactions on Circuits & Systems II Express Briefs · 2025
In this brief, we propose a low-area-cost fault-aware high-reliability Polar decoder VLSI architecture, resisting the unexpected faults randomly occurring in the internal storage elements. As for 2048-bit codeword length, our developed triple-mode chip can be well-reconfigured to perform SC decoding and SCL decoding with the list size (L) of 2 or 4. In the ASIC implementation with TSMC 40-nm multi-Vt CMOS technology, the total core area of our work only occupies 0.769 mm2 in chip layout, operating at a maximum frequency of 666.67 MHz. As compared with other state-of-the-arts, only our chip work can support high-reliability capability under 7.4% area overhead only.