Zero Area Overhead Based Scan-Chain Watermarking
Ashwin CS, Suchismita Roy · 2024
Preventing the illegal use of Intellectual Property (IP) cores remains a crucial challenge for the semiconductor industry. Hardware watermarking has emerged as a practical and widely adopted solution to address this issue by verifying the authorship of the design, thereby detecting IP piracy. For a watermarking scheme to be robust, it must ensure easy detectability and be resilient against various attacks. In this paper, we propose a novel scan chain-based watermarking technique to protect hardware intellectual property (IP) against unauthorised usage and counterfeiting. The proposed method leverages the inherent properties of scan chains used in design-for-testability (DFT) to embed a unique watermark within the hardware design. By utilising genetic algorithms for optimal scan chain reordering and watermark embedding, our approach ensures minimal impact on the hardware's performance and testability. Experimental results demonstrate the robustness and effectiveness of the proposed watermarking scheme in various scenarios.