Area Efficient and High Speed 8x8 Vedic Multiplier Design Using Parallel Prefix Adders
Unnikrishnan M S, B S Supreetha · 2024
High-performance and efficient multipliers are essential for arithmetic operations and digital signal processing. This paper presents an innovative approach to develop an 8x8 Vedic multiplier utilizing Ladner Fischer Parallel Prefix Adders (LF-PPA) instead of the conventional Brent Kung Parallel Prefix Adders (BK-PPA) and Ripple Carry Adder. Ladner Fischer adders, renowned for their regular and modular construction, hold the potential for area efficiency gains. This study investigates the tradeoffs associated with Ladner Fischer adders versus their Brent Kung equivalents to establish a balance between area and speed. Through extensive simulation and verification techniques, the precision and reliability of the proposed design have been ensured. Emphasizing the iterative nature of the design process, fine-tuning methods to optimize parameters and architectures based on simulation results are employed. Synthesis is performed using Xilinx ISE 14.5 with support of Virtex-5 FPGA. The results contribute to the digital arithmetic domain by offering insights into the feasibility and advantages of Ladner Fischer Parallel Prefix Adders in the context of 8x8 Vedic multipliers. The proposed design emerges as a feasible option for scenarios prioritizing space efficiency without compromising overall performance. This study underscores the importance of exploring alternative adder architectures and their impact on multiplier designs in pursuit of optimized hardware implementations for digital arithmetic operations.