64-Bit ALU Design Using Reversible Gates
Sri. C. MURALI MOHAN, T. Swathi · INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT · 2025
The implementation of reversible gates to build a 64-bit Arithmetic Logic Unit (ALU) is a promising contribution to the area of quantum computing as well as low-power digital circuit design. Reversible logic gates provide the benefit of not losing information throughout the process of computation (unlike traditional irreversible gates), which leads to energy being dissipated less frequently. The purpose of designing reversible logic is to decrease the power consumption and heat dissipation challenges present in modern Very Large Scale Integration (VLSI) design. The 64-bit ALU architecture has shown to improve computational efficiency by decreases in quantum cost, garbage outputs, and constant inputs, giving further credibility to it in the field of advanced computing systems in the future. The goal of this project is to execute arithmetic and logical operations through the use of reversible logic while still decreasing power consumption and delay. The constructed ALU utilizes reversible gates, while implementing reversible gates like a Fredkin gate, Feynman gate, and CNOT gate to implement favorable operations (addition, subtraction, and multiplication) including logical functions (AND, OR, XOR). The intent is to keep the number of garbage outputs and constant inputs to a minimum - garbage outputs and constant inputs are both important parameters of irreversible gates.