A 128-Stack Multi-Level-Cell NAND Flash based Compute-in-Memory Macro with an Integrated Signed Weight Bitline and Sub-0.15µA Cell Current Programming Accuracy
Yonghwan Hong, Minsu Kim, Chris H. Kim · 2025
A 3D NAND flash compatible compute-inmemory array featuring multi-bit weight storage, 128 NAND layers, a 40-bitline multiply-and-accumulate operation, a new program scheme for minimizing back pattern dependency, and an integrated signed weight bitline scheme was demonstrated in a standard 65 nanometer technology. Combining the proposed circuit techniques, our design achieves a cell current error less than 0.15µA and an inference accuracy within 1.3% (64 stack) and 2.8% (128 stack) of the ideal software results for the VGG-16 neural network architecture and CIFAR-10 dataset.